The present invention relates generally to a high voltage semiconductor device, and more particularly to a high voltage lateral power semiconductor device for a switching power supply, a motor drive, a fluorescent inverter drive and the like.
PWM control method has become widespread for a switching power supply, a motor drive and a fluorescent inverter drive. With respect to a control circuit, there is the need for improving the function, reducing the size and cost, improving the reliability and reducing the electricity consumption. Accordingly, there is an increasing demand for a power IC in which high voltage power elements are integrated. A power IC for a power supply, which drives commercial 100-200V, requires an element breakdown voltage of 700V in order to drive a transformer. To facilitate the integration with a control part, the power IC must be lateral and its substrate and drift region has a high resistivity (a low impurity concentration) (Journal of Electricity EDD-93-21, P21-29, Toshihiko Uno et al. xe2x80x9cReduction in ON resistance of a high voltage lateral power MOSFET for IPDxe2x80x9d). With respect to the layout of the device, opposite electrodes must be arranged in the teeth of comb pattern in order to improve a current driving performance per unit area. To improve the integration degree, however, the radius of curvature is small at a corner part of the teeth of comb pattern. This induces the local concentration of electric fields, and lowers the breakdown voltage by about 20%.
FIG. 18 is a plan view of a conventional high voltage lateral power semiconductor device as a first example, and FIG. 19 is a cross-sectional view taken along line A-B of FIG. 18. As shown in FIG. 19, this semiconductor device is constructed in such a manner that an N well 2 and a P base 3 are formed on a p type substrate with a high resistivity of about 150 xcexa9cm. The N well 2 has a surface impurity concentration of 1xc3x971016/cm3, and a diffusion depth of 6 xcexcm. The amount of donor in the N well 2 is 1xc3x971012/cm2. The total amount of donor in the N well, the resistivity of the P substrate and the distance of the drift region are optimized to achieve a high breakdown voltage.
The P base, which forms a source region, has a surface concentration of 3xc3x971016/cm3, and a diffusion depth of 6 xcexcm. A threshold voltage of a power MOS is determined according to the surface concentration. Then, a thermal oxide film 4 with a thickness of 0.6 xcexcm, and a polysilicon gate 6 is formed through a gate oxide film 5 of 25 xcexcm. An n+ diffused layer with a surface concentration of 1xc3x971020/cm3, and a diffusion depth of 0.2 xcexcm is formed in a source 7 and a drain 8, and a contact P+ diffused layer (with a surface concentration of 5xc3x971019/cm3, and a diffusion depth of 0.5 xcexcm) 9 is formed on the surface of the P base. An interlayer insulating film 10 is formed and a contact hole 11 is opened, and then a source electrode 12 and a drain (gate) electrode 13 are formed.
In this prior art, the device is shaped like the teeth of comb having a straight portion 20 in which the P base region 3 forming the source region and the drain 8 are parallel to one another if they are viewed prospectively, and corner parts 21, 22 having the same interval between the P base region 2 and the drain 8 as the parallel interval of the straight portion 20. If there is the need for an actual output current capacity of 2-5A class, a channel width must be not less than 50 mm and the number of teeth of comb must be more than 10 and less than 20.
In this prior art, the straight portion 20 and an end portion of the teeth of comb pattern at the corner part have the cross-sectional structure shown in FIG. 19. If the radius of curvature is 100 xcexcm, the breakdown voltage is 800V. If, however, radius of curvature is 12.5 xcexcm, the electric fields are heavily concentrated at the corner part. This lowers the breakdown voltage to 600V. Therefore, the radius of curvature must be not less than 50 xcexcm in order to ensure the breakdown voltage of 700V. More specifically, a device pitch cannot be reduced, and it is therefore impossible to improve the current driving performance per unit area. Accordingly, the breakdown voltage of the power semiconductor device is 700V and the ON resistance per unit area is about 90 xcexa9/mm2 in this prior art.
FIG. 20 is a cross-sectional view of a conventional high voltage lateral power semiconductor device as a second example. A plan view thereof is the same as FIG. 18.
In the second example, an N well 2A is formed on a p type substrate 1 with a high resistivity of about 150 xcexa9cm, and a P base 3A is formed inside the N well 2A. The N well 2A has a surface impurity concentration of 1xc3x971016/cm3, and a diffusion depth of 6 xcexcm. The amount of donor in the N well 2A is 1xc3x971012/cm2. The total amount of donor in the N well 2A, the resistivity of the P substrate 1 and the distance of the drift region are optimized to achieve a high breakdown voltage. The P base 3A has a surface concentration of 3xc3x971016/cm3, and a diffusion depth of 2 xcexcm. A threshold voltage of a power MOS is determined according to the surface concentration. A p type surface region 14 is formed between the P base 3A and an n+ drain. The p type surface region 14 has a surface impurity concentration of 5xc3x971016/cm3, and a diffusion depth of 1 xcexcm.
In the prior art of the second example, a straight portion and a corner part 22A (see FIG. 18) at an end portion of the teeth of comb have the cross-sectional structure shown in FIG. 20. If the radius of curvature is 100 xcexcm, the breakdown voltage is 800V. If, however, radius of curvature is 12.5 xcexcm, the electric fields are heavily concentrated at the corner part. This lowers the breakdown voltage to 600V. For this reason, the radius of curvature cannot be reduced to not less than 50 xcexcm in order to ensure the breakdown voltage of 700V. More specifically, the device pitch cannot be reduced, and it is therefore impossible to improve the current driving performance per unit area. Accordingly, the ON resistance per unit area is as high as 60 xcexa9/mm2 if the radius of curvature is set at 50 xcexcm in order to ensure the breakdown voltage of 700V.
To address this problem, a semiconductor device of the third example is known in which a drain corner part has an electric field reliving structure as disclosed in Japanese Patent Provisional Publication No. 6-244412.
FIG. 21 is a plan view showing a prior art of the third example, and FIGS. 22(a)-22(c) are partial cross-sectional views showing principal parts of FIG. 21. FIG. 22(a) is a cross-sectional view taken along line A-B of FIG. 21, FIG. 22(b) is a cross-sectional view taken along line C-D of FIG. 21, and FIG. 22(c) is a cross-sectional view taken along line E-F of FIG. 21. In this structure, the end portion 22A at the drain corner part in FIG. 18 is shortened as shown in FIG. 21, and the p type surface region 14 in this region is eliminated by a length L and a width W to form an n type surface region 16. The width W of the eliminated region is optimized to thereby relieve the electric fields at the corner part.
In this structure, however, the relief of the electric fields must be adjusted within the width of the p type surface region 14 in the N well 2A of at the drain corner end portion. Since the N well 2A has a relatively high surface impurity concentration, the range of optimum values of the width W is very narrow and this increases the dispersion in the breakdown voltage. For this reason, the radius of curvature needs to be 30 xcexcm in order to ensure the breakdown voltage of 700V, and thus, the ON resistance per unit area is lowered by only 15%. It is therefore impossible to satisfactorily lower the ON resistance.
As stated above, the conventional semiconductor devices have disadvantages because the electric fields are concentrated at the corner part and the breakdown voltage cannot be sustained if the integration degree is improved for the purpose of improving the current driving performance. It is therefore difficult to improve the current driving performance by improving the integration degree.
It is therefore an object of the present invention to provide a semiconductor device, which is able to relieve the concentration of the electric fields generated at the corner part and the like even if the integration degree of the device is improved, and therefore easily improves the current driving performance by improving the integration degree.
To accomplish the above object, a semiconductor device is provided which broadens the interval in a voltage applied region at a corner part, provides a region with an optimized impurity concentration in that part, and fills a depletion layer to thereby relieve the concentration of electric fields.
More specifically, the present invention is directed to a semiconductor device, in which a second-conductivity-type well is formed on a first-conductivity-type semiconductor substrate and a second-conductivity-type diffused region is formed inside the well, and in which a first-conductivity-type diffused region is formed at a desired position on the first-conductivity-type semiconductor substrate, the first-conductivity-type diffused region and the second-conductivity-type diffused region having straight portions with an uniform interval, a corner part being formed at an end portion of the straight portions, the semiconductor device characterized in that: at the corner part in the second-conductivity-type diffused region, the interval between the first-conductivity-type diffused region and the second-conductivity-type diffused region is larger than the interval between the straight portions, and the conductivity characteristics in a larger interval region are different from those of the second-conductivity-type well along a predetermined width in order to relieve concentration of electric fields at the corner part. This arrangement relieves the concentration of electric fields at the corner part and the like, and therefore easily improves the current driving performance by improving the integration degree.
According to the present invention, a first-conductivity-type region is formed along a predetermined width in the interval region. With this arrangement, a depletion layer is spread into the first-conductivity-type region provided in the interval region. For example, the first-conductivity-type semiconductor substrate can be used as the first-conductivity-type region in the interval region, and this extremely simplifies the structure by eliminating the necessity of adding any impurities. In this case, the high-resistivity first-conductivity-type semiconductor substrate is sued as the first-conductivity-region in the depletion layer, and this enables the uniform relief of the electric fields to obtain an optimum value of the interval region in a relatively wide range. This makes it possible to easily adjust the relief of the electric fields.
According to the present invention, a second-conductivity-type region is formed along a predetermined width in the interval region, the second-conductivity-type region having a different impurity concentration from that of the second-conductivity-type well. With this arrangement, the depletion layer can be spread by adjusting the impurity concentration of the second-conductivity-region, and this enables the uniform relief of the electric fields and achieves the high breakdown voltage.
If, for example, the n type second-conductivity-region is formed of phosphorous P, the phosphorous is deposited on an interface of an oxide film and a silicon substrate by thermal treatment, and therefore, the surface of the substrate has a high concentration. Thus, the surface can be composed of high-concentration n type impurities, and this controls the shift in the breakdown voltage caused by plus electric charge generated inside the oxide film and on the surface of the device.
According to the present invention, a second-conductivity-type region and a first-conductivity-type surface layer formed thereon are formed along a predetermined width in the interval region, the second-conductivity-type region having a different impurity concentration from the second-conductivity-type well along a predetermined width. This arrangement achieves the high impurity concentration of each conductivity-type region, and controls the shift in the breakdown voltage caused by the plus electric charge.
According to the present invention, a plurality of first-conductivity-type regions and second-conductivity-type regions is formed along a predetermined width in the interval region. This arrangement achieves the high impurity concentration of each conductivity-type region, and controls the shift in the breakdown voltage caused by the plus electric charge.
According to the present invention, a first-conductivity-type diffused surface layer is formed on a surface of the second-conductivity-type well. With this arrangement in which the first-conductivity-type diffused surface layer is formed on the surface of the second-conductivity-type well, the amount of impurities is increased in the second-conductivity-type well. This reduces a drift resistance if the device has a high breakdown voltage.
According to the present invention, a second-conductivity-type region and a first-conductivity-type surface layer formed thereon are formed along a predetermined width in the interval region, the second-conductivity-type region having a different impurity concentration from the second-conductivity-type well along a predetermined width. With this arrangement in which the first-conductivity-type diffused surface layer is formed on the surface of the second-conductivity-type well, the impurity concentration of the second-conductivity-type well can be increased to thereby reduce the drift resistance of the second-conductivity-type well if the device has a high breakdown voltage. Moreover, the impurity concentration of the second-conductivity-type region and the first-conductivity-type surface layer can be increased to thereby to control the shift in the breakdown voltage caused by the plus electric charge.
According to the present invention, the first-conductivity-type diffused region and the second-conductivity-type diffused region are opposite to one another and form the teeth of comb pattern, and the corner part is formed at an end portion of the teeth of the comb pattern. This arrangement broadens a channel width, and increases the current driving performance.
According to the present invention, the first-conductivity-type diffused region is formed inside the second-conductivity-type well. With this arrangement in which the first-conductivity-type region is formed inside the second-conductivity-type well, the impurity concentration of the drain region adjacent to a channel can be increased when a MOSFET is formed. This reduces a drain resistance.
According to the present invention, the first-conductivity-type diffused region is formed outside the second-conductivity-type well. This arrangement increases a channel length to thereby control the operation of parasitic bipolar transistors provided between the N well, the P base and the source.
According to the present invention, a second-conductivity-type source region is formed inside the first-conductivity-type region, and the second-conductivity-type diffused region formed inside the second-conductivity-type well is a MOSFET that functions as a drain region. This arrangement makes it possible to relieve the concentration of electric fields generated at the corner part and the like even if the integration degree of the device is improved. This realizes a high voltage MOSFET device that is capable of easily improving the current driving performance by improving the integration degree.